The present invention relates to integrated circuits, and in particular to flash memory cells with vertical transistors.
Semiconductor memories are widely used for data storage. As logic devices, the density of memory cells is typically limited by a minimum lithographic feature size imposed by lithographic processes used during fabrication. However, increasing demand for data storage capacity of semiconductor memories requires a reduction in the size of access FETs and storage capacitors in memory cells.
Flash memory, a member of the non-volatile class of memory storage devices, retains its data even when power is removed, and achieves higher density and lower cost through traditional silicon process scaling techniques, such as feature size reduction. In addition, flash memory also provides superior electrical reading, erasion, and programming in the host system, without requiring removal. Currently, flash memory devices are widely found in PCs and cellular phones and are a key component of the emerging digital imaging and audio markets.
FIG. 1A shows a physical layout of a conventional flash memory cell, a modified NMOS transistor with a floating gate. In a flash memory cell, a thin layer of oxide is deposited as tunnel oxide on top of a channel area on a p-type silicon substrate (P—Si). A layer of poly-silicon is deposited on top of the tunnel oxide as a floating gate (FG). Another layer of oxide is deposited on top of the floating gate (FG) as an isolation layer. A front metal-based gate is deposited on top of the isolation oxide for voltage control, i.e. a control gate (CG). The silicon substrate (P—Si) beside the gate structure is doped with n-type ions to serve as source/drain regions (S/D). Because the floating gate is insulated by oxide, negative charge thereon is contained, even if power is interrupted.
FIG. 1B shows a circuit symbol of the flash memory cell in FIG. 1A. The raw states of a flash memory comprise 1's, since each floating gate carries no negative charges. FIG. 1C shows a partial matrix of flash memory cells. Word lines (WL) are disposed along an X-axis and bit lines (BL) along a y-axis. Flash memory cells at the intersection have control gates connected to WLs (i.e. the decoded address), drains connected to BLs, and sources connected to SLs (source lines). The SLs are connected to a common ground. The voltage combinations applied to WL and BL define an operation: read, erase, or program.
Similarly, conventional flash memory cells are also limited by a minimum lithographic feature size. Since there is an increasing demand for high capacity storage devices, there is a need to develop denser flash memory devices.